1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having vertical transistors.
2. Description of Related Art
In recent years, vertical transistors have been proposed to advance finer integration of transistors. A vertical transistor uses, as a channel, a semiconductor pillar extending perpendicular to a principal plane of a semiconductor substrate. Specifically, a vertical transistor includes a semiconductor pillar (a base column or a silicon pillar) formed so as to extend upward from a semiconductor substrate and a gate electrode formed on a side surface of the semiconductor pillar with a gate insulator film being interposed between the gate electrode and the semiconductor pillar. The vertical transistor also includes a drain region formed near a lower portion of the semiconductor pillar and a source region formed at an upper portion of the semiconductor pillar. A gate-lifting pillar (dummy pillar) is provided near the semiconductor (silicon) pillar in order to supply electric power to the gate electrode of the vertical transistor. Such a transistor is disclosed in JP-A-2009-88134, for example.
A vertical transistor requires a smaller space as compared to a planar transistor having a channel arranged in parallel to a principal plane of a semiconductor substrate. Furthermore, even if the channel length (gate length) is increased, an area required for a vertical transistor does not increase. In other words, a vertical transistor can suppress the short channel effect without any increase of a space required. Additionally, a vertical transistor can achieve full depletion of a channel and can advantageously provide a good S value (Subthreshold swing value) and a large drain current.